The present invention relates to processing systems having multiple processing modules and to processing modules for such processing systems.
In processing systems having multiple processing modules, the multiple processing modules are typically mounted in an array of connectors on a backplane. As well as providing a support structure for the processing modules, the backplane provides communication paths between the processing modules and also to other parts of the processing system. The speed of communication the backplane can provide is limited by its need to serve all of the elements connected via the communication paths.
The invention finds particular application to fault tolerant multi-processor systems, where each processing module forms a replaceable processor module of the system. In such systems, a very high bandwidth is required between the processor modules in order to provide for the exchange of data and control information between the processors to check the operation of the processors and to ensure that they remain in lockstep.
With the continuing increases in processing power of processing systems, the overall performance of such systems is becoming more and more limited by the speed of communication available over such backplane communication paths. Accordingly, it would be desirable if the bandwidth available for communication between processing modules could be increased.
One possible method of increasing the available bandwidth is to increase the clock frequency at which the backplane operates. However, increasing the clock frequency leads to significant additional problems including increased electromagnetic radiation, increased unreliability due to possible timing skew, and so on, as will be apparent to one skilled in the art.
The provision of additional connections over the backplane is typically not possible because all available space for connections via the backplane is already allocated. Increasing the density of pathways also leads to increased unreliability due to manufacturing tolerances and timing problems due to capacitive effects between pathways, for example.
In order to reduce communication delays between processing modules via the backplane, and also to minimise the overall size of the processing system, the individual modules are typically arranged in a tight one or two dimensional array with minimal space between them. Moreover, for reasons of mechanical strength and protection and/or to provide electromagnetic shielding, the modules typically have a substantially cuboidal housing of metal or metallised material. As a result, it would not be practicable to provide further electrical connections between the modules for a number of reasons. For example, there is typically insufficient space between modules securely to make additional connections after mounting of the modules. Also, as the modules could be inserted in different relative dispositions in the array of backplane connectors, the provision of some form of automatic electrical connection would be problematical and unreliable. A further problem where the modules include electromagnetic shielding is that it is typically not possible to have openings or apertures large enough for additional electrical connectors without compromising electromagnetic shielding requirements.